1. Field of the Invention
The invention relates to data processing systems and more particularly to a method and apparatus for initiating an early instruction fetch to an external bus controller simultaneously with checking an on-chip cache for the instruction.
2. Description of the Related Art
Many recent processors run at peak rates of one instruction per clock cycle, but they can execute only one instruction stream at any given time. The processor described in application Ser. No. 07/630,499, can execute up to 3 instructions in a clock cycle. It can make use of look-ahead information in the program sequence up to 4 instructions ahead of the current program counter. It can also switch between independent program streams on a cycle-by-cycle basis with 0-clocks overhead. All this makes this processor extremely hungry for instructions at its micro-bus, so an on-chip instruction cache is used to hold frequently used instructions.
Traditionally, processors with an on-chip instruction cache (I-cache) first access the on-chip I-cache before attempting to fetch instructions from the off-chip bus. If the fetch-access requested misses the on-chip instruction cache, then the access is sent to the external bus controller for an off-chip access. This serial process (first check the on-chip cache, then go off-chip) causes extra delay in getting the requested instruction data when the access misses the on-chip cache. This extra delay in getting the instructions slows the processor down when running applications that frequently miss the on-chip I-cache.
It is an object of the present invention to provide an instruction fetch unit that will supply multiple instructions per clock to a micro bus from several sources on dem and in response to an address from a program counter by initiating an instruction fetch to an external bus controller simultaneously with checking an on-chip cache for the instruction.